`ifndef PC_REG_V
`define PC_REG_V


`include "defines.v"

module pc_reg(
	input  wire 		 				clk,
	input  wire 		 				rstn,
	input  wire[`InstAddrWidth - 1 : 0] jump_addr_i,
	input  wire 		 				jump_en,

	output reg[`InstAddrWidth - 1 : 0] 	pc_o
);

always @(posedge clk or negedge rstn) begin
	if(rstn == 1'b0) begin
		pc_o <= 32'b0;
	end
	else if(jump_en) begin
		pc_o <= jump_addr_i;
	end
	else begin
		pc_o <= pc_o + 4'd4;
	end
end

endmodule


`endif // PC_REG_V